{ ===================================================== }
{    74LP74                                             }
{ ===================================================== }
logicname 74LP74

{ ----------------------------------------------------- }
{    手続き譜                                           }
{ ----------------------------------------------------- }
procedure dreg
input  D;
input  PR,CLR;
output Q;
bitr   q;

   if (!CLR)
      q=0;
   else
      if (!PR)
         q=1;
      else
         q=D;
      endif
   endif

   Q=q;

endp

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  DA,DB;
input  PRA,PRB;
input  CLRA,CLRB;
output PQA,PQB;
output NQA,NQB;
bitn   qa,qb;

   qa=dreg(DA,PRA,CLRA);
   qb=dreg(DB,PRB,CLRB);

   PQA=qa;
   NQA=!qa;

   PQB=qb;
   NQB=!qb;

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output DA,DB;
output PRA,PRB;
output CLRA,CLRB;
output PQA,PQB;
output NQA,NQB;
bitr   tc[5];

   part TTL(DA,DB,PRA,PRB,CLRA,CLRB,PQA,PQB,NQA,NQB)
 
   tc=tc+1;

{ - - - - - - - - - - - - - - - - - - - - - - - - - - - }
{    A                                                  }
{ - - - - - - - - - - - - - - - - - - - - - - - - - - - }
   if (tc>5)
      if (tc==11)
         CLRA=0;
      else
         CLRA=1;
      endif
   endif

   if (tc==7) PRA=0; else PRA=1; endif

   if ((tc>9)&(tc<14)) DA=1; endif

{ - - - - - - - - - - - - - - - - - - - - - - - - - - - }
{    B                                                  }
{ - - - - - - - - - - - - - - - - - - - - - - - - - - - }
   if (tc>5)
      if (tc==11)
         CLRB=0;
      else
         CLRB=1;
      endif
   endif

   if (tc==7) PRB=0; else PRB=1; endif

   if ((tc>9)&(tc<14)) DB=1; endif
ende

endlogic