{ ===================================================== }
{    74LP77                                             }
{ ===================================================== }
logicname 74LP77

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  G12,G34;
input  D[4];
output PQ[4];
bitr   q[4];

   if (G12)
      q.0:1=D.0:1;
   else
      q.0:1=q.0:1;
   endif

   if (G34)
      q.2:3=D.2:3;
   else
      q.2:3=q.2:3;
   endif

   PQ=q;

ende

{ ----------------------------------------------------- }
{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output G12,G34;
output D[4];
output PQ[4];
bitr   tc[5];

   part TTL(G12,G34,D,PQ)

   tc=tc+1;

   if ((tc>5)&(tc<10)) G12=0; else G12=1; endif
   if ((tc>5)&(tc<12)) G34=0; else G34=1; endif

   if ((tc>6)&(tc<18)) D=5; else D=10; endif

ende

endlogic