{ ===================================================== }
{    74LP86                                             }
{ ===================================================== }
logicname 74LP86

{ ----------------------------------------------------- }
{    実効譜                                             }
{ ----------------------------------------------------- }
entity TTL
input  A[2],B[2],C[2],D[2];
output Y1,Y2,Y3,Y4;

   Y1 = A.0 ^ A.1;
   Y2 = B.0 ^ B.1;
   Y3 = C.0 ^ C.1;
   Y4 = D.0 ^ D.1;
ende

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{    機能実行譜                                         }
{ ----------------------------------------------------- }
entity sim
output A[2],B[2],C[2],D[2];
output Y1,Y2,Y3,Y4;
bitr   tc[5];
   
   part TTL(A,B,C,D,Y1,Y2,Y3,Y4)

   tc=tc+1;

   switch(tc)
      case 3:  A=0;
      case 4:  A=1;
      case 5:  A=2;
      case 6:  A=3;

      case 7:  B=0;
      case 8:  B=1;
      case 9:  B=2;
      case 10: B=3;

      case 11: C=0;
      case 12: C=1;
      case 13: C=2;
      case 14: C=3;

      case 15: D=0;
      case 16: D=1;
      case 17: D=2;
      case 18: D=3;
   endswitch

ende

endlogic