{\{ ==================================== \}} {\{ 論理譜 \}} {\{ ==================================== \}} logicname sample {\{ ------------------------------------ \}} {\{ 手続き \}} {\{ ------------------------------------ \}} procedure seg7out input DATA[4]; output SEGDATA[7]; bitn sega; bitn segb; bitn segc; bitn segd; bitn sege; bitn segf; bitn segg; SEGDATA.0=sega; SEGDATA.1=segb; SEGDATA.2=segc; SEGDATA.3=segd; SEGDATA.4=sege; SEGDATA.5=segf; SEGDATA.6=segg; switch(DATA) case 0: sega=1; case 1: sega=0; case 2: sega=1; case 3: sega=1; case 4: sega=0; case 5: sega=1; case 6: sega=1; case 7: sega=1; case 8: sega=1; case 9: sega=1; endswitch switch(DATA) case 0: segb=1; case 1: segb=1; case 2: segb=1; case 3: segb=1; case 4: segb=1; case 5: segb=0; case 6: segb=0; case 7: segb=1; case 8: segb=1; case 9: segb=1; endswitch switch(DATA) case 0: segb=1; case 1: segb=1; case 2: segb=1; case 3: segb=1; case 4: segb=1; case 5: segb=0; case 6: segb=0; case 7: segb=1; case 8: segb=1; case 9: segb=1; endswitch switch(DATA) case 0: segc=1; case 1: segc=1; case 2: segc=0; case 3: segc=1; case 4: segc=1; case 5: segc=1; case 6: segc=1; case 7: segc=1; case 8: segc=1; case 9: segc=1; endswitch switch(DATA) case 0: segd=1; case 1: segd=0; case 2: segd=1; case 3: segd=1; case 4: segd=0; case 5: segd=1; case 6: segd=1; case 7: segd=0; case 8: segd=1; case 9: segd=0; endswitch switch(DATA) case 0: sege=1; case 1: sege=0; case 2: sege=1; case 3: sege=0; case 4: sege=0; case 5: sege=0; case 6: sege=1; case 7: sege=0; case 8: sege=1; case 9: sege=0; endswitch switch(DATA) case 0: segf=1; case 1: segf=0; case 2: segf=0; case 3: segf=0; case 4: segf=1; case 5: segf=1; case 6: segf=1; case 7: segf=0; case 8: segf=1; case 9: segf=1; endswitch switch(DATA) case 0: segg=0; case 1: segg=0; case 2: segg=1; case 3: segg=1; case 4: segg=1; case 5: segg=1; case 6: segg=1; case 7: segg=0; case 8: segg=1; case 9: segg=1; endswitch endp {\{ ------------------------------------ \}} {\{ 手続き \}} {\{ ------------------------------------ \}} procedure updownbcd input RESET; input EN; input DIR; input FCIN; output Q[5]; bitr q[4]; bitn fcout; Q.0:3=q; Q.4=fcout; if (RESET) q=9; else if (EN) if (FCIN) if (DIR) switch(q) case 9: q=0; default: q=q+1; endswitch else switch(q) case 0: q=9; default: q=q-1; endswitch endif else q=q; endif else q=q; endif endif if (DIR) switch(q) case 9: fcout=1; endswitch else switch(q) case 0: fcout=1; endswitch endif endp {\{ ------------------------------------ \}} {\{ 実効譜 \}} {\{ ------------------------------------ \}} entity main input RESET; {\{ 初期化 \}} input PSW; {\{ 押しボタン \}} input DIR; {\{ 増減 \}} input LCDCOM; {\{ LCDのCOM端子 \}} output SEG7OUTA[7]; {\{ 7セグメント1番目桁 \}} output SEG7OUTB[7]; {\{ 7セグメント2番目桁 \}} bitn en; {\{ 有効 \}} bitn qa[5]; bitn qb[5]; bitn seg7outa[7]; bitn seg7outb[7]; bitr keytimepulse[2]; bitr keytimer[4]; bitn getkeytime; {} output T0P[4]; T0P=qa.0:3; output T1P[4]; T1P=qb.0:3; output T2P[2]; T2P=keytimepulse; output T3P[4]; T3P=keytimer; output T4P; T4P=getkeytime; {} if (RESET) keytimepulse=0; else if (LCDCOM) switch(keytimepulse) case 0: keytimepulse=1; case 1: keytimepulse=2; default: keytimepulse=keytimepulse; endswitch else keytimepulse=0; endif endif if (RESET|getkeytime) keytimer=0; else if (keytimepulse.0) keytimer=keytimer+1; else keytimer=keytimer; endif endif switch(keytimer) case 10: getkeytime=1; endswitch if (getkeytime) en=PSW; endif if (LCDCOM) SEG7OUTA=!seg7outa; SEG7OUTB=!seg7outb; else SEG7OUTA=seg7outa; SEG7OUTB=seg7outb; endif qa=updownbcd(RESET,en,DIR,1); qb=updownbcd(RESET,en,DIR,qa.4); qa.5=1; qb.5=1; seg7outa=seg7out(qa.0:3); seg7outb=seg7out(qb.0:3); seg7outa.7=1; seg7outb.7=1; ende {\{ ==================================== \}} {\{ 機能実行譜 \}} {\{ ==================================== \}} entity sim output RESET; output PSW; output DIR; output LCDCOM; output SEG7OUTA[7]; output SEG7OUTB[7]; output TC[8]; bitr tc[8]; TC=tc; part main(RESET,PSW,DIR,LCDCOM,SEG7OUTA,SEG7OUTB) tc=tc+1; if (tc<5) RESET=1; endif if (tc>35) DIR=0; else DIR=1; endif LCDCOM=tc.1; PSW=tc.3; ende endlogic