パリティ

logicname sample

{ -------------------------------------- }
{    実効譜                              }
{ -------------------------------------- }
entity parity
input  a[8];
output q[4];
bitn   b4s[4];
bitn   t4s[4];

   switch(a.0:3)   {下4桁の1を数えます。}
      case 0b0000: b4s=0;
      case 0b0001: b4s=1;
      case 0b0010: b4s=1;
      case 0b0011: b4s=2;
      case 0b0100: b4s=1;
      case 0b0101: b4s=2;
      case 0b0110: b4s=2;
      case 0b0111: b4s=3;
      case 0b1000: b4s=1;
      case 0b1001: b4s=2;
      case 0b1010: b4s=2;
      case 0b1011: b4s=3;
      case 0b1100: b4s=2;
      case 0b1101: b4s=3;
      case 0b1110: b4s=3;
      case 0b1111: b4s=4;
   endswitch

   switch(a.4:7)   {上4桁の1を数えます。}
      case 0b0000: t4s=0;
      case 0b0001: t4s=1;
      case 0b0010: t4s=1;
      case 0b0011: t4s=2;
      case 0b0100: t4s=1;
      case 0b0101: t4s=2;
      case 0b0110: t4s=2;
      case 0b0111: t4s=3;
      case 0b1000: t4s=1;
      case 0b1001: t4s=2;
      case 0b1010: t4s=2;
      case 0b1011: t4s=3;
      case 0b1100: t4s=2;
      case 0b1101: t4s=3;
      case 0b1110: t4s=3;
      case 0b1111: t4s=4;
   endswitch

   q=t4s+b4s;   {上と下の1の数をたして全8桁の1の数を出します。}
ende

{ -------------------------------------- }
{    機能実行譜                          }
{ -------------------------------------- }
entity sim
output a[8];
output q[4];
bitr   tc[8];

   part parity(a,q)

   tc=tc+1;

   a=tc;

ende

endlogic